What Does a 2nm Wafer Cost in 2026? Yield & CapEx Data Analysis

A 2nm wafer has no single price. The answer changes with fab utilization, process yield, die size, packaging, financing, and the number of customers sharing the line’s fixed costs.

A practical 2026 model puts capital depreciation alone at roughly $3,704 to $6,667 per good 300 mm wafer under a simplified set of assumptions. Those figures are not total manufacturing cost, foundry selling price, or what a customer ultimately pays for each good packaged die. They cover only the depreciation burden of the fab’s installed capital.

Materials, chemicals, labor, power, maintenance, overhead, financing, packaging, testing, and supplier margins all come afterward.

The basic 2nm wafer cost model

The starting point is straightforward:

Cost per good wafer = Total wafer cost / (actual wafer starts × wafer yield)

The important word is actual. Suppose a fab has nameplate capacity of 1.2 million 300 mm wafer starts per year. That is its theoretical output at full production—not necessarily the number it runs.

Actual starts are:

Nameplate capacity × utilization

If utilization is 75%, the fab starts 900,000 wafers. At 70% wafer yield, it produces 630,000 good wafers.

Consider a simplified fab with:

• $40 billion in depreciable assets;
• a 10-year depreciation period;
• 1.2 million annual wafer starts at 100% utilization;
• zero residual value.

Annual depreciation is $4 billion. If the line runs at full nameplate capacity, the capital depreciation per good wafer is:

Again, these are depreciation-only figures for good 300 mm wafers. They should not be presented as the market price of a 2nm wafer.

Utilization makes the result worse quickly. At 70% utilization and 70% yield, the same fab produces:

1.2 million × 70% × 70% = 588,000 good wafers.

Annual depreciation per good wafer becomes about $6,803, before any operating expense is added.

Yield and utilization also behave differently. A defect problem reduces the number of good wafers from each run. Idle tools spread the same annual depreciation across fewer starts. A shortage of inspection capacity, for example, can leave an expensive lithography tool available while the overall line still fails to reach planned output.

Wafer yield is not the same as die yield, either. A wafer can pass process inspection yet produce fewer usable chips because of defect location, die size, edge exclusion, or design sensitivity.

Cost per good die = Total wafer cost / (usable die per wafer × die yield × packaging yield)

That distinction matters most for large AI and networking chips. A 2nm wafer may contain relatively few large dies, and one defect can eliminate a valuable device. For a small mobile or connectivity chip, the cost per packaged die may be far lower even when both products use the same wafer process.

A practical total-cost sensitivity check

The following table adds an illustrative operating cost of $2,500 per actual wafer start for materials, labor, utilities, maintenance, and factory overhead. It excludes financing, packaging, testing, masks, and customer-specific engineering. The $40 billion fab and 10-year depreciation assumptions remain unchanged.

This is not a market forecast. It shows why early production can look uneconomic even when the eventual process target is attractive. The fab is paying for the same buildings and tools while running fewer starts, losing more wafers, and absorbing higher engineering costs.

A foundry selling price will normally be higher than this manufacturing cost. It must cover corporate overhead, risk, profit, capacity reservation, mask charges, and the cost of supporting the customer’s design. Customer cost per good packaged die goes higher still when assembly, test, advanced packaging, and final yield are included.

High-NA EUV is a line investment, not a scanner purchase

High-NA EUV scanners are often discussed at roughly $300 million or more per system, with market estimates for some configurations reaching above €350 million. ASML does not publish a universal list price for every system, so these numbers should be treated as estimates rather than catalog prices.

The scanner is only the beginning. A High-NA installation may require:

• floor reinforcement and vibration control;
• upgraded power, cooling, vacuum, and hydrogen systems;
• new metrology and inspection tools;
• masks and pellicles;
• installation, qualification, and service;
• process-development labor;
• yield-learning losses during ramp.

ASML’s 2025 annual report provides the company’s reported EUV shipments, revenue, capacity plans, and system outlook. Its public product information also shows that throughput depends on operating conditions rather than a single guaranteed number. Uptime, recipe mix, maintenance, exposure conditions, and resist performance all affect actual wafer output.

High-NA depreciation should not be charged evenly across every wafer start. The right allocation follows the tool’s use:

High-NA cost per wafer = Annual High-NA cost / annual High-NA exposure events × High-NA layers per wafer

Annual exposure events depend on scanner capacity, uptime, and utilization. A wafer requiring four High-NA layers should carry roughly twice the High-NA exposure charge of one requiring two, assuming comparable process conditions.

Facility modifications and shared metrology should be allocated separately. Some costs support the entire line; others belong directly to the High-NA process module.

High-NA can reduce multi-patterning, mask count, etch steps, and defect opportunities. Whether it saves money depends on the complete flow. The scanner must achieve useful uptime, the new process must yield, and the avoided steps must be valuable enough to repay the additional capital.

A sensible investment test compares:

• scanner and facility depreciation;
• service and spare-parts expense;
• process-development labor;
• qualification downtime;
• expected savings from removed process steps;
• incremental good-die output.

A technically superior tool can still be a poor investment if it spends too much time waiting for recipes, masks, inspection, or downstream capacity.

Regional economics and foundry scale

Location changes the hurdle rate. A prospective European Commission semiconductor cost model assigns the EU a production-cost index of 100, compared with 53 for Taiwan and 50 for South Korea. The figures should be read as a structural comparison, not as a quote for a particular company or fab.

The model reflects more than wages. Electricity, supplier density, construction lead times, financing, compliance, logistics, maintenance response, and accumulated process experience all feed into the result. The European Commission’s semiconductor policy and industry resources provide the relevant policy context; the specific index should be linked to the underlying staff analysis when published.

Subsidies lower net capital expenditure, but they do not automatically improve day-to-day fab performance. A grant can reduce the financing burden without lowering power prices or shortening the time needed to qualify a new process.

For investment decisions, separate three numbers:

1. Gross CapEx: the full construction and equipment bill.
2. Net CapEx: gross CapEx less grants, tax credits, and partner contributions.
3. Risk-adjusted cost: net CapEx plus delay, utilization, yield-ramp, financing, and operating risks.

The third figure is the one that determines whether the project can earn an acceptable return.

Scale matters just as much. TSMC spreads process-development costs, engineering staff, spare parts, masks, and depreciation across a broad external customer base. That aggregation helps keep expensive leading-edge capacity busy.

Intel’s model is different. It combines internal product demand with an external foundry business. That can provide tighter design-manufacturing integration, but it also creates a utilization challenge. If internal demand does not fill the line and external customers ramp slowly, depreciation per good wafer rises. Intel’s annual filings discuss underutilization, capital intensity, impairment risk, and the economics of building new process technology.

How to use the model

Use separate ramp, learning, and mature cases rather than one optimistic forecast:

• Ramp: 50%–65% utilization and 40%–60% yield.
• Learning: 65%–80% utilization and 60%–80% yield.
• Mature: 80%–95% utilization and 80%–95% yield.

Then stress-test the variables that move the result:

• a two-year construction delay;
• a 10-point utilization decline;
• slower yield learning;
• higher interest rates;
• lower wafer pricing;
• packaging constraints;
• weak external demand;
• High-NA uptime below plan.

Keep those risks visible. A board should be able to see whether a cost increase comes from idle tools, poor yield, expensive power, financing, or packaging—not from one unexplained risk premium.

For investors, useful signals include utilization commentary, yield trends, depreciation expense, capacity additions, and customer commitments. For operators, the key measure is simpler: good output per dollar of installed capital.

A 2nm fab becomes commercially compelling only when it can turn exceptional equipment into a steady flow of good wafers and packaged products. Until then, the headline node and the scanner price tell only a small part of the story.

Frequently Asked Questions

How much does a 2nm wafer cost in 2026?

There is no verified public price. In the simplified model above, capital depreciation ranges from about $3,704 to $6,667 per good 300 mm wafer at full utilization and 90% to 50% yield. Total manufacturing cost is higher, and foundry selling price is higher again.

How much does High-NA EUV add per wafer?

It depends on scanner depreciation, uptime, utilization, facility costs, and the number of High-NA layers on each product. The cost should be allocated by actual exposure events, not spread equally across every wafer start.

Why can Taiwan or South Korea produce wafers more cheaply than Europe?

Lower financing costs, dense supplier networks, strong fab scale, lower operating friction, and accumulated process expertise all contribute. Subsidies can narrow the gap, but they do not remove those structural differences.

Is TSMC’s model more efficient than Intel’s?

TSMC benefits from broad customer aggregation and high external utilization. Intel can gain from design-manufacturing integration, but its leading-edge economics are more exposed to internal demand, external customer adoption, and underutilization.