Transmon T1 T2 Surface Code: Is 1 ms Fault-Tolerant in 2026?

A transmon whose best qubit reaches $1.68\ \text{ms}$ makes a striking headline. But if the chip’s median $T_1$ is only a few hundred microseconds and its two-qubit error remains above the surface-code budget, the headline tells an incomplete story.

For fault-tolerant computing, the useful question isn’t how long the best qubit survives in isolation. It’s whether the entire processor maintains low, stable error through repeated entangling gates, measurements, resets, and decoding cycles.

Key takeaways

• A 1 ms $T_1$ isn’t enough: Surface-code performance depends on the effective error per operation or cycle, not one relaxation time.
• The spread matters: Recent transmon results range from median $T_1$ values near $100$–$425\ \mu\text{s}$ to a reported maximum of $1.68\ \text{ms}$.
• Benchmark the processor, not the record: Median and lower-percentile coherence, two-qubit error, leakage, readout, reset, and drift are more useful than a single best measurement.

What a 1 ms transmon actually buys you

A qubit’s energy-relaxation time, $T_1$, measures how quickly an excited state decays. It’s fundamental, but it doesn’t capture every way a computation can fail.

The related coherence time $T_2$ measures the decay of phase information:

Coherence relationship: $\frac{1}{T_2}=\frac{1}{2T_1}+\frac{1}{T_\phi}$

Here, $T_\phi$ is the pure-dephasing time. If $T_2$ approaches $2T_1$, relaxation is close to the limiting process. A much shorter $T_2$ indicates substantial dephasing.

Recent experiments show why a maximum value needs context. A 2025 high-coherence transmon study reported a median $T_1$ of about $425\ \mu\text{s}$, a best value of $666\pm33\ \mu\text{s}$, a median echo time near $541\ \mu\text{s}$, and a best echo result around $1.06\ \text{ms}$. A separate 2025 Nature study reporting 1.68 ms in a two-dimensional transmon platform pushed the record considerably higher.

Those results represent real progress. They also show the difference between a record device and a usable processor population.

For a 5 GHz transmon, a $1\ \text{ms}$ lifetime corresponds to a quality factor of roughly:

Quality factor: $Q\approx2\pi fT_1\approx3.1\times10^7$

That’s an impressive number. A processor, however, doesn’t spend its life idling. It runs microwave pulses, entangling gates, measurement sequences, resets, and sometimes excursions into noncomputational states.

Consider the difference between $1\ \text{ms}$ and $300\ \mu\text{s}$. The former is about 3.3 times longer, but neither number directly gives a fault-tolerant gate error. If a two-qubit gate lasts $200\ \text{ns}$, a $300\ \mu\text{s}$ $T_1$ gives a rough relaxation exposure of:

Relaxation exposure per gate: $t_g/T_1=200\ \text{ns}/300\ \mu\text{s}\approx6.7\times10^{-4}$

That is only one contribution. Control distortion, leakage, crosstalk, residual $ZZ$ coupling, dephasing, and correlated events may dominate the measured two-qubit error.

How $T_1$, $T_2$, and gate errors enter a surface code

The phrase “surface-code threshold” can suggest that there’s a single $T_1$ value at which fault tolerance suddenly starts. There isn’t.

Threshold estimates are often discussed in the approximate $10^{-3}$ to $10^{-2}$ range, but the number depends heavily on the noise model, decoder, code layout, syndrome schedule, and whether it refers to gate, measurement, or full-cycle error. Reviews such as Fowler et al. provide useful context, but no threshold number transfers automatically to real hardware.

A simplified cycle-level budget is:

Physical cycle error: $p_{\text{cycle}}\approx p_{T_1}+p_{T_\phi}+p_{\text{control}}+p_{\text{leakage}}+p_{\text{readout}}+p_{\text{correlated}}$

The ratio $t_{\text{cycle}}/T_1$ estimates only the relaxation term. It says nothing about population leaking into $|2\rangle$, measurement confusion, reset failure, or a thermal event affecting several qubits.

That’s why excellent single-qubit randomized benchmarking doesn’t guarantee a successful surface-code experiment. Repeated two-qubit gates under simultaneous operation are usually the harder test.

A useful first comparison is the coherence-to-gate ratio:

Coherence-to-gate ratio: $N_{\text{coh}}\approx T_{2,\text{echo}}/t_{\text{2Q}}$

With $T_{2,\text{echo}}=500\ \mu\text{s}$ and a $200\ \text{ns}$ entangling gate, the ratio is about 2,500 gate durations. That indicates storage headroom, not 2,500 high-fidelity gates. The figure becomes meaningful only alongside measured gate error, leakage, crosstalk, and simultaneous-operation data.

For a surface-code processor, ask:

• What is the two-qubit error during the actual syndrome schedule?
• How much leakage accumulates over repeated cycles?
• What are measurement and reset errors?
• Does performance degrade when neighboring qubits operate together?
• How stable are the numbers over the full experiment?

A one-hour stability record can be more valuable than a five-minute record showing a spectacular best point.

Why thermal noise and TLS defects still matter at 10 mK

At 5 GHz, the energy scale is approximately $hf/k_B=0.240\ \text{K}$. Ideal thermal occupation is tiny at dilution-refrigerator temperatures:

The catch is that a refrigerator’s mixing-chamber thermometer doesn’t prove the chip or resonator is at the same temperature. Microwave lines carry radiation, resonators retain photons, package modes couple to the device, and readout can create nonequilibrium excitations.

Residual resonator photons are particularly troublesome. They shift the qubit frequency and introduce photon shot noise, shortening $T_2^*$ and making coherence depend on recent measurement activity. One 3D-transmon experiment reported residual cavity occupation below roughly $2\times10^{-4}$. That’s a small population, but it can still matter when the coherence target approaches a millisecond.

The engineering response is broader than “cool it more”: use appropriate attenuation and infrared filtering, isolate amplifier outputs, thermalize resonators and wiring, control package modes, and limit heat deposited at the mixing chamber.

Two-level-system defects create a different problem. A TLS near a qubit or resonator can absorb energy intermittently, making $T_1$ jump between favorable and unfavorable values as frequency or environmental conditions change. The result is a time-series problem, not a single-number problem.

Measure $T_1$ repeatedly over hours, sweep frequency where possible, track frequency drift, and report the median and lower percentiles. A qubit that stays above $300\ \mu\text{s}$ for a day may be more useful than one that briefly reaches $1.5\ \text{ms}$ before dropping to $100\ \mu\text{s}$.

Echo and CPMG sequences can extend measured coherence by filtering slow frequency noise. An echo $T_2$ exceeding $T_1$ is therefore possible: echo removes part of the low-frequency dephasing contribution, while $T_1$ still limits energy relaxation. It does not mean relaxation has been overcome, nor does it guarantee that an algorithm receives the same protection.

The five metrics engineers should report

A processor report should prioritize measurements that connect coherence to the workload:

1. Median and lower-percentile $T_1$, $T_2^*$, and echo $T_2$ across the active qubits.
2. Two-qubit error during simultaneous operation, ideally under the intended syndrome schedule.
3. Leakage, measurement, and reset error, not just computational-subspace randomized benchmarking.
4. Syndrome-cycle duration and thermal conditions, including residual resonator occupation where available.
5. Drift over the complete experiment, including cooldown-to-cooldown variation and TLS-related jumps.

A useful supplementary metric is a stability-adjusted coherence ratio:

Stable coherence ratio: $C_{\text{stable}}=P_{10}(T_{2,\text{echo}})/t_{\text{2Q}}$

It doesn’t replace measured gate error, but it discourages reporting only the most favorable qubit at the most favorable frequency.

The same discipline applies to error mitigation. Zero-noise extrapolation can help on short, stable circuits when noise can be scaled consistently. It’s much less comfortable when TLS defects cause unpredictable changes in $T_1$. A slightly shorter but stationary coherence time may be easier to work with than a higher value that drifts throughout the run.

For anyone comparing transmon T1 T2 surface code results, the practical priority is clear: favor the lower tail of the distribution, active-cycle two-qubit fidelity, leakage control, and long-run stability over a solitary record.

A $1\ \text{ms}$ $T_1$ proves that transmons can store quantum information for surprisingly long periods. It does not prove that a processor is below the surface-code threshold. That requires stable, gate-level evidence under the thermal, control, and scheduling conditions the code will actually face.

Frequently asked questions

Is a 1 ms $T_1$ enough for fault-tolerant computing?

No. It can reduce relaxation error, but fault tolerance also depends on dephasing, two-qubit gates, leakage, readout, reset, correlated noise, and drift. The useful benchmark is effective error per syndrome cycle.

How many two-qubit gates fit within coherence time?

For $T_{2,\text{echo}}=500\ \mu\text{s}$ and a $200\ \text{ns}$ gate, the rough ratio is 2,500 gate durations. That isn’t a fidelity prediction; leakage, crosstalk, control error, and dephasing determine the actual result.

Does cooling from 20 mK to 10 mK guarantee better coherence?

No. Ideal thermal occupation is already extremely low for a 5 GHz qubit at those temperatures. TLS loss, residual photons, quasiparticles, dielectric loss, flux noise, or poor thermalization may be the real limit.